This invention concerns an apparatus and a method of measuring alignment accuracy (overlay accuracy) for measuring failures such as misalignment or defocusing occurring upon exposure and etching of patterns in a production step of producing aimed substrates by forming circuit patterns on substrates such as semiconductor manufacturing steps, liquid crystal display device manufacturing steps and manufacturing steps of a printed circuit board, as well as a method of manufacturing semiconductor devices for producing semiconductor devices by analyzing misalignment or the like and adopting countermeasure therefor, as well as a system thereof.
Heretofore, for producing semiconductor devices, thickness of deposition films, dimension after exposure or after etching or misalignment with lower layer patterns were measured on every production steps for semiconductor devices and process conditions were set such that they were within predetermined ranges.
In this case, when deposition films or etching patterns formed on a semiconductor substrate (wafer) are not within a predetermined range, failure rate of semiconductor chips in the wafer is increased to deteriorate the yield of semiconductors (ratio for good products).
Thickness of the deposition film or the size of the pattern upon exposure and the etching exceeds the predetermined range by fluctuation of various process conditions such as pressure of reaction gas, temperature of substrate supports, voltage applied upon plasma generation, intrusion of impurities into the process gas, focal position upon exposure and overlay level upon exposure, or erroneous manual input of the process conditions.
Also in similar production steps for liquid crystal display devices, when process conditions such as pressure of reaction gas and overlay level upon exposure fluctuate, manufactured products can not be used as display devices. The situation is also identical in the manufacturing steps of printed circuit boards in which fluctuation of process conditions causes short and connection failure of circuit patterns.
As one of methods of measuring alignment accuracy for semiconductor substrates of this type, a method of measuring misalignment of alignment marks on a semiconductor substrate by irradiating light onto semiconductor substrate and producing semiconductors while changing the process parameters if they are not within a predetermined range has been described in Japanese Patent Laid-Open No. H10-2533250.
In the prior art described above, misalignment for three chips, five chips or nine chips in a wafer is measured but the subject of the measuring distribution of the misalignment within the wafer has not been recognized. Accordingly, there is no concept of measuring the distribution of the misalignment in a wafer and, therefore, it has not yet been attained.
Further, introduction of CMP (Chemical Mechanical Polishing) step or the like to the manufacturing steps for semiconductor devices results in a problem that the contrast of images for alignment mark is low, making the measurement for the misalignment difficult. The prior art described above has a subject that measurement for misalignment does difficult by the detection of images having at low contrast from the alignment mark.